Abstract– energy efficient active block that set up

Abstract– This paper presents the design of high
speed 4-bit Arithmetic Logic Unit (ALU). ALU is one of the most important parts
of a processor which is designed to perform the arithmetic and logic
operations. The two important features are considered for designing an ALU are
increasing the speed and reducing power consumption. The overall performance of
the system will depend on the speed of the different modules used in the design.
However increasing the performance of ALU also increases the power consumption.
To achieve the low power consumption, high speed ALU is proposed using 1-bit
hybrid full adder. The performance of proposed ALU is verified using Tanner EDA
V13 with CMOS technology of 0.25µm. The simulated results show that the proposed
design reduces the number of transistors that will result in lesser area occupation
and reduces the power consumption comparing with the existing ALU’s.

Key terms
: ALU, Hybrid adder, power consumption,

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Portable devices such as mobile phones,
notebooks, laptops etc. use batteries for their operations. The most important
feature of modern electronics is low power and energy efficient active block
that set up the implementation of all devices that are operated by battery. In
a modern electronics, designing of accurate and fast arithmetic circuit which
leads to long lasting battery operated designs. Arithmetic circuits are the
significant building block in Very Large Scale Integrated (VLSI) circuits and
efficient implementation of these circuits will enhance the performance of the
entire system. The Arithmetic Logic Unit (ALU)
the basic arithmetic and logical operation. ALU
is a fundamental component of all CPU and it is an integral part of the execution
unit. CPU can be more powerful, but it also can
consume more energy and creates more heat depending on how the ALU is designed. Therefore, it is important to
balance between power consumption, speed and complexity of the ALU. At high speed, the CPU consumes more power and
power dissipation is high. There are many different power reducing techniques
being used to design low power, high-performance chips based on Complementary
Metal-Oxide-Semiconductor (CMOS)
such as reducing voltage, load capacitance or switching frequency of the output
node. By reducing the supply voltage (Vdd), the power consumption is
minimized which results in quadratic improvement in the power dissipation of a CMOS circuit.



Processor is the part of digital system that comprised of
a number of registers and the digital functions that contains arithmetic,
logic, shift and transfer micro operations. Processor unit combined with a
control unit that supervises the sequence of micro-operations called a central
processing unit. Processor unit executes simple and basic micro-operations such
as add and shift. Other operations such as multiplication, division are
performed in conjunction with the control unit. The control unit is designed to
deliver the sequence of control signals to perform other operations which are
not included in the basic micro-operation.The digital function that implements
the micro operations on the information stored in the processor registers are
commonly called as Arithmetic Logic Unit. To perform micro operations, the
control routes the source information from the registers into the inputs of the
ALU. The ALU receives the information from the register and perform the given
operation specified by the control. The result of the operation is the
transferred to a destination register.




The  arithmetic and bitwise
operations on  binary numbers are
performed by the combinational digital electronic circuit is called Arithmetic Logic Unit. An ALU is presented in the Central Processing Unit (CPU) of computers, Floating
Point Unit (FPU) and Graphic Processing Unit (GPU). A single CPU, FPU or
GPU contains multiple ALUs. The ALU has a number of selection lines to select a
particular operation to be implemented in the unit. Fig. 1.1 shows the logic
symbol of 4-bit ALU.  The four data
inputs form A are
combined with the four inputs from B
to generate an operation at the F. The data inputs from A and B
are combined together to produce an arithmetic operation at the output F. The
arithmetic and logic operations are differentiated by the mode select input S2.
The S1 and S0  are
the two function select inputs that specify the particular arithmetic
or logic operation to be generated. The three selection variables are possible
to specify four arithmetic operations and four logic operations. The input
carry Cin enters into the full adder circuit in the least
significant bit position. The output carry Cout comes from the full
adder circuit in the most significant position. The least significant position
of the input carry in an ALU is frequently used as a fourth selection variable
to double the number of arithmetic operations. There are three stages in the
ALU design.

A.            Design of Arithmetic Circuit

The basic element
of an arithmetic section of an ALU is a parallel adder. Full adder is cascaded
to form a Parallel adder. To obtain the different types of arithmetic
operations the data inputs to the parallel adder are controlled. Single full adder is capable of adding two one bit
numbers and input carry. Two or more full-adders are connected to form parallel
binary adders. In arithmetic circuit, the four full adder stages are
implemented using 4-bit parallel adder. The output carry of each adder is
connected to the input carry of the next higher-order adder as indicated. These
are called internal carries.


In most of the system, the fundamental
computational unit is adder. The overall speed performance of the entire system
mostly depends on delay. The propagation delay of the carry signal is minimized
which depends on the speed response of an adder by reducing the path length of
the carry signal. Different types of logic styles are used to design the full adder. Each design style has its own merits and demerits. Classical designs of
full adder normally use only one logic style for the whole full adder design.
The most important logic styles used in the conventional adders are Classical
Complementary Metal Oxide Semi-conductor, Complementary pass transistor logic
and Transmission Gate. For 1-bit Full adder, single unit is good. By
cascading the adders, it requires more area which results in more delay hence the
performance degrades drastically. Optimized design is necessary to avoid the
degradation problem in the circuit and it results in low power consumption,
reduced delay in critical path. The combination of more than one logic style in
the adder is called Hybrid Full Adder. The hybrid CMOS logic style is being
used to provide high performance (low power, low area, and low delay) circuits.
High performance is obtained by reducing the number of transistor consequently;
the number of power dissipating nodes and area are reduced.


The arithmetic addition is achieved when one
set of input receives a binary number A and other set of inputs receives a
binary number B and the input carry is maintained at 0. By making Cin=1,
it is possible to add 1 to the sum. The effect of complementing the all the
bits to input B with Cin=0, the output becomes A+, which
is the sum of A plus 1’s complement of B. Adding 1 to the sum by making Cin=1,
then A++1,
which produces sum of A plus the 2’s complement of B. this operation is similar
to subtraction operation if the output carry is discarded. Zero is given to B
terminals then the result becomes A+0=A, adding 1 through Cin, then
A+1 is obtained. Inserting all 1’s to the B terminal produces the decrement
operation A-1.the circuit that control input B to provide function called
one/zero element.


B.            Design of Logic Circuit

The logic micro-operations operate the bits
of the operands separately and treat each bit as binary variable. Some of the Logical
operations are obtained by means of AND, OR, NOT. Two selection lines is used
to select among the four logical operations. In the logical circuit, the four
gates generate the four logical operations such as OR, XOR, AND, NOT. The two
selection variables in the multiplexer select one of the gates for the output. The
combination of logic circuit and arithmetic circuit is used to create one
arithmetic logic unit. The common selection variables S1 and S0
and the third selection variable S2 is used to differentiate between
them. Each stage of the logic and arithmetic circuit outputs enters into the
multiplexer with selection variable S2.When S2=0, the
arithmetic output is selected, but when S2=1, the logic output is
selected by combining this two circuit ALU circuit is designed. It is not the
best way to design the efficient ALU.


C.            Design of Arithmetic Logic Unit

ALU is designed for performing the eight
arithmetic operations and four logic operations. Three selection variables S2, S1, S0
select eight different operations and the input carry Cin is used to
select four additional arithmetic operations. With S2=0, selection variables S1, S0
together with Cin will select the eight arithmetic operations and S2=1, variables S1, S0 select the four logical operations OR, XOR, AND, NOT.
The design of ALU has combinational logic problem, because the unit has a
regular pattern. For designing the one stage ALU, the remaining stages of ALU
is duplicate in it. There are six inputs to the each stage A, B, C, S2,
S1, and S0. There are two outputs to
the each stage F, Ci+1. Each stage performs different kinds of